Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
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United States of America Patent
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Nov 14, 1995
Grant Date -
N/A
app pub date -
Oct 4, 1993
filing date -
Oct 4, 1993
priority date (Note) -
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Abstract
The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.
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