Capacitive coupled summing circuit with signed output
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United States of America Patent
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-
Nov 21, 1995
Grant Date -
N/A
app pub date -
Feb 15, 1994
filing date -
Feb 16, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A summing circuit for executing summing of analog data with sign. The summing circuit includes two serially connected inverters INV1 and INV2, each having a feed back line, and selectively inputs data D1 to D8 to one of the first or the second stages, corresponding to positive/negative sign signals S1 to S8.
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