Content addressable memory having match line transistors connected in series and coupled to current sensing circuit
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United States of America Patent
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Nov 21, 1995
Grant Date -
N/A
app pub date -
Apr 22, 1994
filing date -
Apr 28, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a contents addressable memory for a fully associative cache memory in which address bit values in respect of data to be retrieved from cache are applied to the bit lines of respective columns of cells for comparison with the bit values held by the cells, a match in any one cell is arranged to forward bias a match line device in that cell, the match line devices of a row being connected in cascade, so that if a match is obtained along a row a current path is provided along the row to a respective current sensing circuit to indicate the match.
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