Circuit and method for decreasing the cell margin during a test mode
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United States of America Patent
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Nov 21, 1995
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N/A
app pub date -
Sep 15, 1993
filing date -
Sep 15, 1993
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Abstract
The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.
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