Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions
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United States of America Patent
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Nov 21, 1995
Issued Date -
N/A
app pub date -
Sep 22, 1994
filing date -
Nov 21, 1990
priority date (Note) -
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Abstract
A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch control data regarding operand fetching and operation control data regarding execution of the instruction; an execution unit for receiving the execution control data directly from the instruction decode unit, and executing a predetermined operation based on the operation control data; and an operand fetch unit for receiving the fetch control data directly from the instruction decode unit, and fetching an operand from a source other than registers in the execution unit. The operand fetch unit fetches the operand concurrently with processing in a second cycle, and subsequent cycles if any, of the operation executed by the execution unit and requiring at least two machine cycles for execution.
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