Apparatus and method for controlling the running of a data processing apparatus
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United States of America Patent
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Nov 21, 1995
Issued Date -
N/A
app pub date -
Dec 22, 1992
filing date -
May 27, 1988
priority date (Note) -
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Abstract
An apparatus and method for controlling the bus cycle running time of a data processing apparatus. The apparatus includes a CPU and at least one device such as a memory device, input/output device and the like which receives data from the C. A clock signal supplied to the CPU is varied based on the bus cycle or address within the device which is identified by the CPU for processing of the data. Alternatively, the frequency of the clock signal is varied based on ambient temperature and line voltage conditions. Accordingly, processing speed of the CPU can be varied to accommodate high speed memory devices and slower speed input/output devices.
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