Importance

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Abstract

An MtoL software tool (FIG. 3) automates the process of converting an RTL behavioral model of the integrated circuit into corresponding layout information in a format that can be input directly to a floor planner/block router--the automated MtoL process facilitates iterative logic design including what-if analysis. A conventional RTL behavioral model is modified (40) to include MtoL bounding box and interconnect netlist macros. The resulting modified RTL module tree (42) is input to an MtoL extraction front-end (43) for conversion to an MtoL-formatted MtoL extract tree. A flattening transformation (44) on the hierarchical MtoL extract tree produces a non-hierarchical representation of the block structure together with a terminal interconnect netlist. The MtoL program then generates (45) MtoL layout information comprising a corresponding set of bounding boxes with terminal data and the associated interconnect netlist information, appropriately formatted for input to the floor planner/block router.

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First Claim