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Abstract

A method and apparatus for allowing two or more masters, such as central processing units (CPUs), to read a dynamic random access memory (DRAM) device which includes a cache connected to a main memory block. When a CPU provides a read request, the DRAM has a first logic circuit that compares addresses requested with addresses stored in the cache. If the addresses are the same, the DRAM sends an acknowledge (ACK) signal to that CPU and sends the data to the processor. If the addresses are not the same, the DRAM sends a no acknowledge (NACK) signal to the CPU and transfers the requested data from the main memory block to the cache. The DRAM has a second logic circuit that contains a latch which is set when the DRAM sends a NACK signal and reset when the DRAM sends a subsequent ACK signal. The second logic circuit is connected to the first logic circuit to disable the first logic circuit and prevent a cache fetch from main memory when the latch has been set. The second logic circuit is also connected to a refresh controller of the DRAM to prevent a refresh cycle when the latch is set. Both the first logic circuit and the refresh controller are enabled when the latch is reset.

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First Claim