Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps
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United States of America Patent
Stats
-
Dec 5, 1995
Grant Date -
N/A
app pub date -
Dec 2, 1994
filing date -
Dec 2, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure by forming rectangular recesses in the insulation layer which are subsequently filled during a subsequent metal deposition step which also serves to fill with the same metal vias or contact openings which have been etched through the insulation layer. Subsequent planarization of the deposited metal layer down to the vias or contact openings, i.e. to remove the portions of the metal layer over the insulation layer, leaves the metal in the vias or contact openings and also leaves metal stringers on the sidewalls of the rectangular recess which then serve as fusible links (fuses) which are then connected to one or more metal lines thereafter formed on the insulation layer.
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