Local clock generator
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United States of America Patent
Stats
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Dec 5, 1995
Grant Date -
N/A
app pub date -
Sep 14, 1992
filing date -
Sep 14, 1992
priority date (Note) -
In Force
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Abstract
A local clock system uses a numerically controlled oscillator referenced to a stable oscillator to generate local clock signals under microprocessor control. Two feedback loops provide inputs to the microprocessor for maintaining synchronization with the external clock reference; a frequency locked and a phase-locked loop. The relatively wide-band frequency-locked loop is used to acquire initial synchronization with the external clock reference when the external clock is restored after having been lost or is switched to a new source. The phase-locked loop has a narrow bandwidth and provides a large attenuation of any jitter on the incoming reference with a resultant low output jitter. The microprocessor provides a hold-over operation upon loss of the external clock reference and when the external reference is restored it slowly adjusts the output clock frequency to match that of the reference, limiting the rate of adjustment so as not to exceed a specified allowable jitter in the local clock output.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| SUMMIT TECHNOLOGY SYSTEMS LP | 401 CITY AVENUE BALA CYNWYD PA 19004 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Davidow, Clifford A | Portland, OR | 13 | 1047 |
| Reilly, Brian F | Hillsboro, OR | 5 | 140 |
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|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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