Method for flattening hierarchical design descriptions
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United States of America Patent
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Dec 5, 1995
Grant Date -
N/A
app pub date -
Jun 12, 1991
filing date -
Jun 12, 1991
priority date (Note) -
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Abstract
The invention describes a method for expanding (flattening) hierarchical descriptions of electronic circuits into flat descriptions. The method is characterized by two processes: one which eliminates feed-through and implicit signals, and another which pre-plans the layout of the flattened data structure before flattening. The flattening process may then take advantage of a number of resulting efficiencies to operate more quickly than present flatteners.
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