Memory architecture and devices, systems and methods utilizing the same
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United States of America Patent
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Dec 5, 1995
Grant Date -
N/A
app pub date -
Sep 12, 1994
filing date -
Sep 12, 1994
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A memory 200 is provided which includes a plurality of self-contained memory units 201 for storing data. A plurality of shift registers 211 are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units 201. Interconnection circuitry 212 is coupled to a parallel data port of each of the shift registers. Control circuitry 208, 213 is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry 212 via the shift register 211 coupled to the selected memory unit 201.
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