Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
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United States of America Patent
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Dec 5, 1995
Grant Date -
N/A
app pub date -
May 9, 1994
filing date -
May 9, 1994
priority date (Note) -
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Abstract
A processing device 107 is provided disposed on a single chip which includes a controller 103 and a memory 104. The controller 103 is coupled to an address bus 202 and a data bus 204. The memory 103 includes a plurality of independently addressable blocks 200 of memory cells, each block 200 coupled to the address bus 202 and having a selected number of output lines coupled to the data bus 204. The controller 103 accesses a location of the selected number of memory cells of a selected one of the blocks 200 through an address presented on the address bus 202.
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