US Patent No: 5,473,575

Number of patents in Portfolio can not be more than 2000

Integrated circuit I/O using a high performance bus interface

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Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1206

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 59 3717
Horowitz, Mark Menlo Park, CA 79 3782

Cited Art

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (4)
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4,449,207 Byte-wide dynamic RAM with multiplexed internal buses 63 1982
4,584,672 CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge 25 1984
4,595,923 Improved terminator for high speed data bus 65 1984
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
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4,649,516 Dynamic row buffer circuit for DRAM 63 1984
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TEXAS INSTRUMENTS INCORPORATED (4)
4,306,298 Memory system for microprocessor with multiplexed address/data bus 51 1979
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UNISYS CORPORATION (3)
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BELL TELEPHONE LABORATORIES, INCORPORATED (2)
4,488,218 Dynamic priority queue occupancy scheme for access to a demand-shared bus 112 1982
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ELXSI CORPORATION, A DE CORP. (2)
4,481,625 High speed data bus system 170 1981
4,519,034 I/O Bus clock 101 1982
 
LOCKHEED MARTIN CORPORATION (2)
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NCR CORPORATION (2)
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APROLASE DEVELOPMENT CO., LLC (1)
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DATAPOINT CORPORATION (1)
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ELPIDA MEMORY, INC. (1)
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F. & S. CORPORATION OF COLUMBUS, (1)
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GENERAL ELECTRIC COMPANY (1)
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HITACHI, LTD. (1)
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IRVINE SENSORS CORPORATION (1)
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KABUSHIKI KAISHA TOSHIBA (1)
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LORAL AEROSPACE CORP. A CORPORATION OF DE (1)
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MOTOROLA, INC. (1)
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NEC CORPORATION (1)
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RAMBUS INC. (1)
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SAXPY COMPUTER, INC., A CA. CORP. (1)
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TERADYNE, INC. (1)
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TEXTRON INC. (1)
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TOKYO SHIBAURA DENKI KABUSHIKI KAISHA (1)
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XEROX CORPORATION (1)
5,023,488 Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines 193 1990
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (3)
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (61)
5,872,736 High speed input buffer 42 1996
5,917,758 Adjustable output driver circuit 80 1996
5,949,254 Adjustable output driver circuit 100 1996
6,115,318 Clock vernier adjustment 71 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 128 1997
6,912,680 Memory system with dynamic timing correction 34 1997
5,940,608 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 110 1997
5,920,518 Synchronous clock generator including delay-locked loop 112 1997
5,898,638 Latching wordline driver for multi-bank memory 9 1997
5,870,347 Multi-bank memory input/output line selection 82 1997
6,014,759 Method and apparatus for transferring test data from a memory array 44 1997
6,173,432 Method and apparatus for generating a sequence of clock signals 92 1997
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6,011,732 Synchronous clock generator including a compound delay-locked loop 201 1997
5,926,047 Synchronous clock generator including a delay-locked loop signal loss detector 67 1997
6,101,197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 134 1997
6,269,451 Method and apparatus for adjusting data timing by delaying clock signal 43 1998
6,016,282 Clock vernier adjustment 216 1998
6,338,127 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same 59 1998
6,349,399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 15 1998
6,279,090 Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device 21 1998
6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 68 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 319 1998
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6,374,360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 32 1998
6,130,855 Latching wordline driver for multi-bank memory 7 1999
6,122,217 Multi-bank memory input/output line selection 10 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 146 1999
6,201,424 Synchronous clock generator including a delay-locked loop signal loss detector 27 1999
6,326,810 Adjustable output driver circuit 46 1999
6,340,904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 26 1999
6,084,434 Adjustable output driver circuit 49 1999
6,519,719 Method and apparatus for transferring test data from a memory array 6 2000
6,378,079 Computer system having memory device with adjustable data clocking 67 2000
6,327,196 Synchronous memory device having an adjustable data clocking circuit 53 2000
6,256,255 Multi-bank memory input/output line selection 7 2000
6,959,016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 13 2000
6,954,097 Method and apparatus for generating a sequence of clock signals 7 2001
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6,499,111 Apparatus for adjusting delay of a clock signal relative to a data signal 42 2001
6,477,675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2001
6,437,600 Adjustable output driver circuit 43 2001
6,952,462 Method and apparatus for generating a phase dependent control signal 21 2001
6,662,304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 125 2002
6,643,789 Computer system having memory device with adjustable data clocking using pass gates 17 2002
6,931,086 Method and apparatus for generating a phase dependent control signal 12 2002
7,016,451 Method and apparatus for generating a phase dependent control signal 4 2002
6,647,523 Method for generating expect data from a captured bit pattern, and memory device using same 12 2002
7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link 11 2003
7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 4 2003
7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 4 2003
7,415,404 Method and apparatus for generating a sequence of clock signals 3 2005
7,418,071 Method and apparatus for generating a phase dependent control signal 7 2005
7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2006
8,181,092 Dynamic synchronization of data capture on an optical or other high speed communications link 0 2006
7,889,593 Method and apparatus for generating a sequence of clock signals 0 2007
7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2008
7,602,876 Method and apparatus for generating a phase dependent control signal 5 2008
8,107,580 Method and apparatus for generating a phase dependent control signal 1 2009
7,954,031 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 0 2009
8,433,023 Method and apparatus for generating a phase dependent control signal 0 2012
 
MICRON TECHNOLOGY, INC. (15)
5,956,502 Method and circuit for producing high-speed counts 12 1997
6,044,429 Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths 43 1997
5,923,594 Method and apparatus for coupling data from a memory device using a single ended read data path 21 1998
6,405,280 Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence 126 1998
6,272,608 Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals 4 1999
6,091,646 Method and apparatus for coupling data from a memory device using a single ended read data path 8 1999
6,415,340 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 8 2000
6,789,175 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 7 2001
6,614,698 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 35 2001
6,611,885 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 3 2001
6,560,668 Method and apparatus for reading write-modified read data in memory device providing synchronous data transfers 7 2001
6,556,483 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths 9 2001
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
 
JAZIO, INC. (10)
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6,151,648 High speed bus system and method for using voltage and timing oscillating references for signal detection 78 1998
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6,327,205 Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate 58 2000
6,513,080 High speed bus system and method for using voltage and timing oscillating references for signal detection 52 2000
6,812,767 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 1 2001
7,123,660 Method and system for deskewing parallel bus channels to increase data transfer rates 8 2002
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7,190,192 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2005
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MOSAID TECHNOLOGIES INCORPORATED (7)
5,946,244 Delay-locked loop with binary-coupled capacitor 121 1997
6,400,641 Delay-locked loop with binary-coupled capacitor 3 1999
6,262,921 Delay-locked loop with binary-coupled capacitor 46 2000
6,256,259 Delay-locked loop with binary-coupled capacitor 0 2000
6,483,757 Delay-locked loop with binary-coupled capacitor 1 2001
6,490,224 Delay-locked loop with binary-coupled capacitor 9 2001
6,490,207 Delay-locked loop with binary-coupled capacitor 22 2001
 
SAMSUNG ELECTRONICS CO., LTD. (6)
6,072,747 High-speed current setting systems and methods for integrated circuit output drivers 25 1998
6,078,536 Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods 9 1998
6,151,264 Integrated circuit memory devices including a single data shift block between first and second memory banks 4 1999
6,256,218 Integrated circuit memory devices having adjacent input/output buffers and shift blocks 3 1999
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6,362,995 Arrangements of interface logic, memory core, data shift and pad blocks for integrated circuit memory devices 7 2000
 
INTEGRATED DEVICE TECHNOLOGY, INC. (4)
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RENESAS ELECTRONICS AMERICA, INC. (3)
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HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
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FREESCALE SEMICONDUCTOR, INC. (1)
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U.S. PHILIPS CORPORATION (1)
5,754,548 Interconnection of local communication bus system 37 1997