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Abstract

A clock signal recovery and synchronization method for the reception of information elements transmitted by an ATM network and a device for the implementation of this method. The clock signal recovery is done by the reception of data elements by means of a local clock signal HL with a frequency equal to the frequency of transmission, the rephasing of the data elements being done only after a wait for the presence, on one and the same phase signal, of several fronts or edges of phase signals of the transmitted data that are coherent with a clock pulse HL and by choosing, as a rephasing signal, the phase signal that meets this condition and that frames the clock pulse. The resynchronization is done by the recognition of the resynchronization word with, possibly, a correction of errors in this word. To rephase the transmitted data, a rephasing circuit uses a delay line for generating phase signals and an edge detection circuit for detecting edges of the phase signals that are coherent with the local clock signal. Preferably, the rephasing circuit includes as many flip-flop register stages as there are errors to be corrected in the data. To resynchronize the data for recognizing a delimiter in a precursor of the data, a resynchronization circuit having a series recognition register is used. To correct errors in the delimiter, the resynchronization circuit preferably has stages of registers offset by one bit and connected by logic gates to the series recognition register.

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First Claim