Circuit structure, semiconductor integrated circuit and path routing method and apparatus therefor
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United States of America Patent
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-
Dec 12, 1995
Issued Date -
N/A
app pub date -
Jun 27, 1994
filing date -
Dec 5, 1988
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An interconnection path layout in a circuit structure having terminals arranged in rows, such as a semiconductor integrated circuit. Paths are first assigned to selected obstruction-free terminal pairs to be interconnected, and then bypasses are assigned to the remaining obstruction-existing terminal pairs to be interconnected. This minimizes the occurrence that the terminal pairs are left un-interconnected. Also, longer vertical paths are assigned to selected terminal pairs with priority. This prevents the reserved paths from becoming obstructions to vertical paths which are later assigned to selected terminal pairs.
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