Error management processes for flash EEPROM memory arrays
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United States of America Patent
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Dec 12, 1995
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N/A
app pub date -
Dec 27, 1994
filing date -
Dec 27, 1994
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Abstract
A method of utilizing circuitry including error detecting and correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by a flash EEPROM memory array.
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