Heuristic digital processor using non-linear transformation
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United States of America Patent
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Dec 12, 1995
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N/A
app pub date -
May 2, 1994
filing date -
Feb 10, 1989
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Abstract
A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a non-linear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least means squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are non-linear and for which explicit mathematical formalisms are unknown.
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