Memory architecture for a three volt flash EEPROM
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United States of America Patent
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Dec 19, 1995
Grant Date -
N/A
app pub date -
Oct 13, 1993
filing date -
Oct 13, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative, Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.
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