Semiconductor memory device employing sense amplifier control circuit and word line control circuit
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United States of America Patent
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Dec 26, 1995
Issued Date -
N/A
app pub date -
Jul 25, 1994
filing date -
May 27, 1992
priority date (Note) -
Expired
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Abstract
A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
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