Semiconductor device manufacturing method

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United States of America Patent

PATENT NO 5480839
SERIAL NO

08179714

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Abstract

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With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA72-34 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI KANAGAWA 2120013 ?2120013

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ezawa, Hirokazu Tokyo, JP 47 956
Miyata, Masahiro Urayasu, JP 28 562

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