Importance

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Abstract

An ADRC encoder generates an ADRC block of 4.times.4 pixels, together with DR, MIN and quantized pixel data (DT) for each block. A macro block formatting circuit generates DR, MIN and DT code data for four ADRC blocks. An adding circuit generates sum data (DR.SIGMA.=DR1+DR2+DR3+DR4 and MIN.SIGMA.=MIN1+MIN2+MIN3+MIN4) of this hierarchical important data in the macro block. The sum data and the important data form which the sum data is formed are distributed and recorded in plural channels. If one of the important data has an error and the remaining important data and the sum data have no error, the important data with the error can be completely corrected. Reproduced pixel data is converted into 3.times.3 block format and an ADRC encoding circuit generates encoded data DTx representing a center pixel and DT data which represents the 8 pixels that surround the center pixel. A timing aligning circuit generates class information formed of the 8 pixel data, the class information being supplied to a memory as a read address for reading out existing-range data and predicted data DTx that had been stored therein during a learning operation. An error is detected by comparing the existing-range data to the encoded data Dtx; and when an error is detected, the predicted data DTx is selected.

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