System and method for error detection and reducing simultaneous switching noise
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United States of America Patent
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Jan 2, 1996
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N/A
app pub date -
Mar 7, 1994
filing date -
Jun 29, 1990
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Abstract
A system and method that reduces the simultaneous switching noise of outputs and the processing delays caused by inductance by using an encoding scheme that results in a net signaling current of substantially zero at each cycle time for the fast parallel switching networks of digital integrated circuit chips and that provides multiple types of error detection.
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