Importance

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Abstract

A digital-to-analog converter includes a digital-to-pulse width converter that converts a desired digital set-point value to a corresponding signal having a pulse width indicative of the desired set-point value. The desired set-point value is fed to a comparator which compares that value to the current count value from a counter that is counting up in ascending integer order. However, instead of presenting the counter output signal lines to the comparator in a normal conventional manner wherein the count value of the counter is presented to the comparator in the conventional ascending integer order, the current value of the counter is presented to the comparator in other than a conventional ascending order. The result is a comparator output signal that transitions more than one time between binary logic levels. This effectively increases the frequency of the comparator output signal. An optimum connection of the counter output signal lines to the comparator can be achieved such that the comparator output signal is divided up into a series of binary logic level pulses that are distributed across the entire cycle time period of the counter. This results in a subsequent output of an integrator that has reduced ripple voltage amplitude.

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First Claim