Method of forming multilayered wiring structure in semiconductor device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 23, 1996
Grant Date -
N/A
app pub date -
Oct 29, 1993
filing date -
Oct 30, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of forming a via structure having good characteristics in a semiconductor device having a multilayered wiring structure includes forming a thin film including a high melting point metal or a high melting point metal compound on at least the side wall of a via hole before a via plug including Al or an Al alloy is formed.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully