Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
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United States of America Patent
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Jan 23, 1996
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Apr 26, 1995
filing date -
Feb 25, 1994
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Abstract
A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c). The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).
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