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Abstract

A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

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