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Abstract

An input bit sequence is converted into n-bit parallel symbol signals each representing one symbol. A shift register stores an 'm' number of the n-bit parallel symbol signals, shifting the n-bit parallel symbol signals one symbol by one symbol and outputting them. At least one selector is operative for sequentially selecting one of the k-th symbol signal and the (m+1)-k-th symbol signal outputted by the shift register in response to a clock signal, where k equals 1, 2, . . . , (m-1)/2. A sampling counter serves to count pairs of successive clock pulses of the clock signal. An Exclusive-OR circuit executes Exclusive-OR operation between the clock signal and an output signal of the sampling counter. At least one first read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A second read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A filter output signal is generated by combining the data output by the first read-only memory and the second read-only memory.

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First Claim