Data processor with real-time diagnostic capability
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United States of America Patent
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Jan 30, 1996
Grant Date -
N/A
app pub date -
Mar 30, 1994
filing date -
Mar 30, 1994
priority date (Note) -
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Abstract
A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as a program address bus. In one mode, the diagnostic circuit (23) halts a central processing unit (CPU) (21) and the FIFO (25) on the occurrence of an event condition, such as a hardware breakpoint. In a second mode, the diagnostic circuit (23) halts the FIFO (25) but keeps the CPU (21) in normal operation. Thus, the contents of the FIFO (25) may be examined through a serial port while the CPU (21) is executing instructions normally.
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