Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes
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United States of America Patent
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Jan 30, 1996
Grant Date -
N/A
app pub date -
Nov 17, 1993
filing date -
Nov 17, 1993
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention relates to a computer system and method of using the same in which add-on memory cards are provided which have error correction code logic on the card and logic to do partial writes of data words. The system has a central processing unit (CPU), and a BUS interconnecting the CPU and the add-on memory cards which are configured to write data and read data from the add-on memory. The system is further configured (either within the CPU or as a separate function) to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU.
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