Apparatus and method for selectively storing error statistics
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United States of America Patent
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Feb 20, 1996
Grant Date -
N/A
app pub date -
Nov 10, 1994
filing date -
Nov 10, 1994
priority date (Note) -
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Abstract
A circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure.
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