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Abstract

A scan converter incorporating a polygon span interpolator with main memory Z buffering. The span interpolator is initiated by instructions from a central processing unit (CPU), and when initiated, the span interpolator inerpolates input color and Z values in parallel. The span interpolator has its own state machine and can, once initiated, operate independent of the clock states of the CPU so that the CPU may process other data. Also, rather than using a dedicated memory as the Z buffer, the Z buffer shares main memory with the CPU. This allows the CPU to send pretranslated initial Z buffer addresses to the span interpolator when the span interpolator is initiated. Subsequent Z buffer addresses and color data addresses may be calculated in parallel with the input color and Z interpolations. Also, since the successive main memory and graphics addresses are known by the software, the memory controller of the invention allows data to be moved directly from main memory to the graphics address without CPU intervention and without having to pass the data through the data caches of the CPU. This greatly improves data transfer efficiencies since the cache penalties present in prior art software scan converters are not present.

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First Claim