Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits
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United States of America Patent
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Feb 20, 1996
Issued Date -
N/A
app pub date -
Oct 27, 1994
filing date -
Nov 6, 1990
priority date (Note) -
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Abstract
A processor emulation system for testing processor operation. First and second identical microprocessors are used together with a target system which includes the main memory. One microprocessor performs an in-system emulation (ISE) function by operating in lock step with the second processor which functions as the master processor. A mode control signal is used to switch the microprocessors between a normal operating mode and an ISE mode. Normal microprocessor signals are outputted on predetermined terminals for the processor in the normal operating mode and the parallel contents of the processor program counter are outputted on the same predetermined terminals when the microprocessor is in the ISE mode. The master processor provides output signals to the target system, with the ISE processor and the master processor both receiving signals from the target system. Operation of the master processor can be ascertained by monitoring the program counter output of the ISE processor.
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