Method of making semiconductor wafers

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5494862
SERIAL NO

08250503

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for a flatter semiconductor wafer free of ORP-observed irregularity and particles generated in handling on the back side of the wafer, in which an alkaline etching is adopted to utilize its advantage and a slight polishing step is combined to a conventional method of this kind. A deficiency of alkaline etching which brings about rougher surface irregularities on the surface of a wafer is eliminated by the use of the step of slight polishing on the back surface after the etching step and the inherent advantage stands without a loss, so that particle generation from the back surface of a semiconductor wafer in handling is much reduced and what's more a flatter semiconductor wafer is realized and a yield of an electronic device fabrication is increased.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • SHIN-ETSU HANDOTAI CO., LTD.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kato, Tadahiro Nishigo, JP 37 551
Masumura, Hisashi Nishigo, JP 44 578
Nakano, Masami Nishigo, JP 26 239
Shima, Sunao Nishigo, JP 2 46

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation