Stacked multi-chip modules and method of manufacturing
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United States of America Patent
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Feb 27, 1996
Issued Date -
N/A
app pub date -
Jun 5, 1995
filing date -
May 22, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
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