Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active
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United States of America Patent
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Feb 27, 1996
Grant Date -
N/A
app pub date -
Dec 30, 1994
filing date -
Dec 30, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
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