Programmable timing logic system for dual bus interface
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United States of America Patent
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Feb 27, 1996
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N/A
app pub date -
Oct 16, 1992
filing date -
Oct 16, 1992
priority date (Note) -
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Abstract
A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number 'n' of times, each for a preset predetermined time period of 'p' microseconds.
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