Synchronous address latching for memory arrays
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United States of America Patent
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Mar 5, 1996
Grant Date -
N/A
app pub date -
Jun 3, 1994
filing date -
Jun 3, 1994
priority date (Note) -
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Abstract
Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
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