Layered features for co-fired module integration
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United States of America Patent
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Mar 12, 1996
Grant Date -
N/A
app pub date -
Aug 26, 1994
filing date -
Aug 26, 1994
priority date (Note) -
Expired
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Abstract
A unitized multilayer circuit structure that includes a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides formed by edges of the dielectric insulating layers and recessed regions formed in one or more one sides of the substrate for use in attaching the unitized multilayer circuit structure to a higher level assembly or for attaching electrical contact circuitry to the unitized multilayer circuit structure.
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