Multi-level logic optimization in programmable logic devices
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United States of America Patent
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Mar 12, 1996
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N/A
app pub date -
Jun 15, 1992
filing date -
Jun 15, 1992
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Abstract
During compiling, a PLD circuit design system inserts nodes in the two level sum-of-product representation of the target circuit at function and procedure boundaries, the carries between bits of arithmetic operators, and the implicit nodes in complicated if statements. The nodes are collapsed providing that the number of unique symbols in the collapsed equations are .ltoreq. than a first predetermined limit, the number of product terms are .ltoreq. a second predetermined limit, and provided the collapsed equations meet constraints depending on whether or not there are inverters or XOR gates available, and whether or not the inverters and XOR gates are fusible. For all registers in the design, equations are generated to fit any possible flip-flop implementation of the register. Both the ON and OFF equations are generated and carried through the entire optimization process so that the DONT CARE information is retained and optimally used in the final equation reduction and device implementation.
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