Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
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United States of America Patent
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Mar 12, 1996
Grant Date -
N/A
app pub date -
Jul 28, 1994
filing date -
Aug 6, 1993
priority date (Note) -
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Abstract
With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.
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- 15 United States
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- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| PS4 LUXCO S A R L | 208 VAL DES BONS MALADES LUXEMBOURG L-2121 |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Miki, Hiroshi | Kokubunji, JP | 72 | 1472 |
| Ohji, Yuzuru | Hinode, JP | 22 | 485 |
| Tachi, Shinichi | Sayama, JP | 52 | 2828 |
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