Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)
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United States of America Patent
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Mar 12, 1996
Grant Date -
N/A
app pub date -
May 31, 1994
filing date -
May 31, 1994
priority date (Note) -
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Abstract
Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.
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