Circuits, systems and methods for improving page accesses and block transfers in a memory system
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United States of America Patent
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Mar 19, 1996
Grant Date -
N/A
app pub date -
Sep 30, 1994
filing date -
Sep 30, 1994
priority date (Note) -
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Abstract
A memory 200 is provided which includes an array 201 of volatile memory cells 202. Addressing circuitry 205, 213 is included for providing access to selected ones of the memory cells 202. Master read/write circuitry 208 is included for reading and writing data into the selected memory cells 202. First slave circuitry 210, 211 is provided for storing data for exchange with the master read/write circuitry 208. Second slave circuitry 210/211 is also provided for storing data for exchange with the master read/write circuitry 208. Control circuitry 206, 214, 215 controls the exchanges of data between the master read/write circuitry 208 and the first and second slave circuitry 210, 211.
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