Memory defect detection arrangement
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United States of America Patent
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Mar 19, 1996
Grant Date -
N/A
app pub date -
Mar 31, 1994
filing date -
Apr 14, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a static random access memory made up of six-transistor memory cells arranged in rows and columns, an arrangement for detecting open circuit or 'soft' defects in the individual inverters of a memory cell includes lowering the supply voltage of a cell under test to overcome the clamping effect of a feedback inverter, applying input signal voltage changes to one of the bit lines associated with the cell, and testing for the expected voltage changes on the other bit line associated with the cell.
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