Microprocessor system for inhibiting access to memory by checking specific address and specific codes

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United States of America Patent

PATENT NO 5500949
SERIAL NO

08237416

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Abstract

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A technique for preventing unauthorized operations in a microprocessor system provided for inhibiting access to a memory by checking specific addresses and codes, includes storing main programs and predetermined specific codes in a first memory, the execution of the specific codes by a user being prohibited; storing user programs in a second memory; respectively writing and reading the main and user programs to and from the first and second memories with a CPU; receiving address information over an address bus into a first check circuit, connected between the CPU and the first and second memories; activating a first check signal in the first check circuit to inhibit access to the first memory when an access instruction to a predetermined prohibited address is supplied by the CPU; receiving data information including instruction codes over a data bus into a second check circuit, connected between the CPU and the first and second memories; activating a second check signal in the second check circuit when instruction codes of the user program are the specific codes; receiving the first and second check signals into an inhibit circuit; and inhibiting access to the first and second memories according to the first and second check signals.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBATOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Saito, Yasuo Yokohama, JP 126 1417

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