Encased electronic circuit with chip on a grid zone of conductive contacts
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United States of America Patent
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Mar 26, 1996
Issued Date -
N/A
app pub date -
Oct 6, 1993
filing date -
May 30, 1989
priority date (Note) -
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status (Latency Note)
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Abstract
The invention relates to the encapsulation of integrated circuits, and more particularly encapsulation in a multi-layer ceramic case. In order to permit the disposition of chips of variable size on a monolithic chip (22, 24, 26) reception site (23, 25, 27) without the risk of having excessively long connection wires between the chip and the conductive regions (44) surrounding the reserved site, it is proposed according to the invention to cover the chip-reception site with a number of mutually insulated conductive contacts which can serve as soldering relays for these connection wires (80, 90, 100). If the chip is large (chip 24) it is bonded or soldered to these contacts; if it is small (chip 22) it is surrounded by relay-contacts.
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