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Abstract

A fiber optic switch interconnects ports (p1-pi) for connection with respective fiber optic channels so that a fiber optic network is realized. Channel modules provide the ports. Each channel module has a port intelligence mechanism for each port and a memory interface system for temporarily storing data passing to and from the ports. A switch module having a main distribution network, an intermix distribution network, and a control distribution network interconnects the memory interface systems and permits exchange of data among the ports and memory interface systems. A path allocation system controls the switch module and allocates the data paths therethrough. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the ports. The destination queues are implemented with a double link list in a single memory configuration so that a separate queue structure in hardware is not necessary. Moreover, the scheduler is implemented with a digital signal processor (DSP) with on-chip memory so that the queues are implemented within the on-chip memory and can be accessed at high speed.

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First Claim