Branch prediction device enabling simultaneous access to a content-addressed memory for retrieval and registration
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United States of America Patent
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Apr 2, 1996
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N/A
app pub date -
May 23, 1995
filing date -
Apr 22, 1991
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Abstract
The branch prediction device of this invention is for use in a pipeline processor where a plurality of instructions are simultaneously processed in various stages, such as the fetch stage, execution stage, memory access stage and register write stage. A two-port branch prediction buffer enables simultaneous operation of the registration and retrieval processes so that a previously registered address can be obtained during the same clock pulse as registration of another branch address occurs.
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