Adaptive DRAM timing set according to sum of capacitance valves retrieved from table based on memory bank size
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United States of America Patent
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Apr 2, 1996
Grant Date -
N/A
app pub date -
Nov 29, 1994
filing date -
Nov 29, 1994
priority date (Note) -
In Force
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Abstract
Timing is set for DRAM memory access in a computer by polling the DRAM memory banks, calculating capacitive load by accessing a prestored table of capacitive load versus DRAM size, and assigning wait states according to calculated capacitive load by accessing a prestored formula. In one embodiment, wait states are assigned in increasing increments for increasing total capacitive load. In an alternative embodiment, timing is assigned bank by bank. Control routines are preferably a part of a system BIOS.
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