Coprocessor executing pipeline control for executing protocols and instructions

United States of America Patent

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Apr 2, 1996
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N/A
app pub date
Feb 5, 1992
filing date
Apr 17, 1987

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Expired

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Abstract

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

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Patent Owner(s)

Patent Owner	Address
HITACHI LTD	TOKYO JAPAN

International Classification(s)

G06F:ELECTRIC DIGITAL DATA PROCESSING

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Asai, Takeshi	Hitachi, JP	35	258
Kaziwara, Hisashi	Hitachi, JP	9	156
Kida, Hiroyuki	Hitachi, JP	24	294
Morinaga, Shigeki	Hitachi, JP	61	1241
Nakagawa, Norio	Kodaira, JP	35	537
Ohba, Mamoru	Hitachi, JP	7	51
Tatezaki, Junichi	Kodaira, JP	9	152
Watabe, Mitsuru	Katsuta, JP	66	853

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Coprocessor executing pipeline control for executing protocols and instructions

Number of patents in Portfolio can not be more than 2000

United States of America Patent

07830460

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PATENT NO	5504912
SERIAL NO	07830460
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07830460

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